A Low Power Signal Detection and Pre-synchronization Engine for Energy-aware Software Defined Radio

SDR enables cost-effective multi-mode terminals but still suffers from significant energy penalty when compared to dedicated hardware solutions. At system level, this energy bottleneck can be leveraged by capitalizing on the opportunistic partitioning and energy-scalable design of both hardware and software architectures. This yields MPSOC platforms where specific engines are dedicated to classes of functions that relate in their computation characteristics and in their duty cycle. In case of burst-based signal reception, detection functions have high duty cycle and hence need ultra low power implementation. Besides, signal synchronization as close as possible to the ADC is desired to free the system bus of signal-less data samples, with direct impact on the system performance and energy. A specific, still programmable ultra low power detection and presynchronization engine targeted to IEEE802.11a/g/n and IEEE802.16e signals is designed in 90nm CMOS. Results show that detectability is guaranteed with a minimal standby power of 1.1 mW, valid signal detection and presynchronization consumes 228nJ while false trigger by a blocker account for 300nJ.